This invention relates to a method for polishing a surface of a wafer by CMP (chemical-mechanical polishing) and to a method for dressing a polishing pad which is used in such CMP.
Chemical-mechanical polishing (CMP), a combination of chemical and mechanical polishing, is an attractive polishing process for planarizing wafers incorporating therein semiconductor integrated circuits, to such an extent that the wafers are provided with almost perfect surface flatness. In a typical CMP technique, a wafer to be polished is mounted onto a polishing pad attached to a platen. The wafer is then rotated, during which a slurry-like abrasive liquid (dispersion of a colloidal silica in a liquid) is supplied between the wafer and the polishing pad, to polish a surface of the wafer.
SOG (spin-on-glass) and etch back are known in the art as a process for planarizing an upper surface of a film such as an interlayer dielectric film of a wafer. In the former process a wafer is spin-coated with a glass solution prepared by dissolution of glass in an organic solvent. In the latter process a film of photo resist is deposited on an interlayer dielectric film and these films are thereafter subjected to simultaneous etch back processing. The CMP process has the advantage over these two processes in that wafers can be planarized more perfectly because the CMP process combines both chemical polishing and mechanical polishing. However, the current technology of the CMP process is not satisfactory. Achieving ideal planarity everywhere in a wafer is still difficult and there is yet room for improvement in the CMP process. Various approaches have been made with a view to improving the uniformity of in-wafer planarity.
One of the approaches is set forth in Japanese Patent Publication (KOKAI) No. 8-339979. This application describes a technique for supporting a wafer lower surface with the aid of fluid, to improve the in-wafer planarity uniformity.
Another approach is described in Japanese Patent Publication (KOKAI) No. 9-225812. This application provides means for maintaining the degree of planarity at an adequate level while performing a CMP process, to improve the in-wafer planarity uniformity.
The following Preston equation is known and is generally used to calculate the CMP polishing rate (Rpo). EQU Rpo=k*P*V,
where k is the Preston coefficient, P is the pressure, and V is the polishing pad/wafer relative speed.
In order to improve in-plane uniformity of the polishing rate, based on the Preston equation, equalization in time quadrature of V (the polishing pad/wafer relative speed) at any points on the wafer is desired. In other words, it has been determined from the Preston equation that such equalization is achieved at an arbitrary point on the wafer to provide best in-plane polishing rate uniformity if both a polishing pad and a wafer rotate at the same speed.
However, CMP is a combination of chemical polishing and mechanical polishing, which makes, in actual process, variations in polishing state complicated. It is difficult to constantly place a polishing pad in an ideal state during a period of polishing. As described in a paper reported in VLSI Multilevel Interconnection Conference (1997), pp. 175-179, not every condition derived from the Preston equation yields best in-plane polishing rate uniformity. Although some reasons why the best conditions sometimes happen to differ from the Preston equation-based conditions may be pointed out, no novel guidelines for improving in-plane polishing rate uniformity are proposed in the foregoing paper.
For example, when mounting a polishing pad of closed-cell-foam type polyurethane onto a platen, the inventors of the present invention believe that the polishing rate varies for the following mechanical reason.
The closed-cell-foam type polyurethane polishing pad, as illustrated in FIG. 10, has at its surface a great number of recess portions with a diameter in a range of 50-100 .mu.m. The recess portions result from the breaking of closed cells at the surface, and a slurry-like abrasive is held in the recess portions. During polishing, the abrasive is supplied between a polishing pad and a wafer little by little. If polishing debris, formed as a result of polishing of the wafer and the pad, is collected in a recess portion, or if recess-portion blocking occurs locally owing to the load of the wafer, polishing is not performed on a portion of the wafer corresponding to such a recess portion filled with polishing debris. Because of the foregoing, the polishing pad will undergo a local variation in polishing rate, resulting in a drop in overall polishing rate. To cope with this problem, the surface of the polishing pad is grounded with a dressing disk having abrasive particles such as diamond after the polishing pad has been used for a certain length of time. This allows the entire polishing pad to become re-activated, and there are formed new recess portions at the surface. However, to date, it is difficult to completely prevent clogged recess portions and deterioration in planarity between one dressing and the next dressing.
The inventors of the present invention noted that the following points suggest that the foregoing in-pad local polishing rate variation adversely affects uniformity of the wafer planarity.
Specifically, after a polishing pad is subjected to a dressing process, it sometimes occurs that grains of diamond, dettached from a dressing disk and then remaining on a polishing pad, produce in the wafer a deep, large scratch visible to even the naked eye. This scratch was observed and the observation result shows that the size of the scratch is large and deep as compared with those of the diamond grain. The reason why such a large scratch is created may be explained as follows. A grain of diamond, cut into a wafer, passes through a fixed trajectory many times with pad/wafer relative rotational motion, as a result of which the original micro scratch gradually develops until visible to the naked eye.
To summarize, in the case there exists the foregoing non-uniformity of polishing rate in a polishing pad, if there is locally created a low polishing-rate portion in the polishing pad which frequently passes through a corresponding wafer region (in other words if a fixed point on the wafer frequently passes through a specific region on the polishing pad) the variation in polishing rate of the polishing pad gradually promotes deterioration in wafer planarity uniformity. However, the relationship between polishing pad rotation and wafer rotation has been little considered in conventional CMP processing.